1. Field of the Invention
The present invention relates to communication equipment and, more particularly, to power supply control method and circuit for reduction of power consumption in the communication equipment such as packet-based communication equipment and the like.
2. Description of the Related Art
To preserve the global environment, while energy conservation measures have been considered and studied at the global level, legislation for energy conservation and carbon dioxide emissions reduction has also begun to be discussed in individual nations. Although what is generally thought of as the subject of such study and discussion is the energy consumption involved in transportation, distribution, and manufacture in many cases, attention is beginning to be also paid to the increasing energy consumption related to information communication equipment and network infrastructure as well as electronic equipment such as computers and servers.
Electronic equipment, such as computers and servers, spends relatively large amounts of time in a state of not performing operational processing (in general, referred to as “idle state”). Therefore, the average power consumption can be reduced by suppressing the power consumed in the idle state. That is, electronic equipment can highly effectively contribute to a reduction in equivalent carbon dioxide emissions.
On the other hand, information communication equipment is required to always keep a state capable of communicating data, although a transition is being made from analog communications to digital communications. Therefore, there is a premise that information communication equipment cannot tolerate the idle state, unlike electronic equipment such as computers and servers. That is, information communication equipment has no other way of reducing the average power consumption but by lowering the value of normal operating power.
Accordingly, mainstream techniques for reducing power consumption in information communication equipment are mostly those from a device-technology perspective, such as higher levels of large-scale integration of electronic parts, and lower operating voltage owing to finer electronic parts.
However, in reality, as to the effect of the lower operating voltage owing to a finer electronic part, the operating voltage has already fallen below one volt, and the pace of operating voltage reduction is slowing down. Moreover, the effect of the larger-scale integration is also on a downward trend. Therefore, it is more and more difficult to achieve a significant reduction of power consumption in information communication equipment.
Further, as an electronic part become finer to fall below 90 nm in size, leakage current is increased to have a non-negligible value. Accordingly, despite individual device venders' efforts at the device technology-based studies, the power consumption in the idle state is significantly increasing.
On the other hand, measures from the viewpoint of circuit design are also studied. Attempts have been made step by step to achieve lower power consumption by employing asynchronous circuitry and schemes, which use no clock, in place of clock synchronous circuitry and schemes, which are the mainstream of the internal circuitry of an electronic part.
To a device for performing power control in the above-described communication equipment, it is possible to apply the techniques described in JP2002-182807 and JP2003-271267. According to the technique described in JP2002-182807, pieces of power control information and various operational conditions of a processor stored in a power table are rewritable. According to the technique described in JP2003-271267, the power consumed inside a processor is controlled depending on effective addresses. Particularly in a case of a processor that executes a program consisting of multiple parts, the power consumed inside the processor is controlled based on those program parts which are currently executed.
However, these techniques for reducing power consumption in information communication equipment aim at obtaining an effect of reducing the average power consumption by reducing the normal operating power and the power consumption in the idle state. Accordingly, there is a problem that ordinary developers have no opportunity to use the asynchronous circuitry and schemes, as development techniques, for general electronic parts such as, for example, application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs), since development tools for design and evaluation have not been improved yet.
As for packet-based communication, packet-based communication equipment receives a varying amount of traffic and performs sequential processing of received packets. However, it is known that packet-based communication is not performed at all times and therefore the packet-based communication equipment may be kept in the state capable of data communication without transmitting or receiving data for a considerably long time. Therefore, the intervals between input packets are long and the amount of input traffic is small, so that there is a period of time when no packet exists in packet processing sections. Even during such a period when packet processing operation is not required, power is supplied from the power supply section. Since power is supplied even when each packet processing section does not need to perform packet processing, power consumption called “standby power” is produced, which means power is constantly consumed by each packet processing section. Accordingly, the average operating power consumption is large and is not reduced even at the time of small traffic. It is apparent that the techniques described in JP2002-182807 and JP2003-271267 cannot solve such a problem.
For power consumption reduction in such communication equipment, JP2004-236350 discloses a radio communication device which can effectively reduce power consumption depending on a reduction in the amount of signal processing during periods of no user data. More specifically, the radio communication device disclosed in JP2004-236350 is provided with a baseband signal processing section for processing a frame-structured signal, which includes a plurality of signal processing engines and data buffers connected in series. A signal processing engine checks whether data to be processed in a following signal processing engine is left or not. Based on the result of the check, a control engine controls a power supply controller to reduce power consumption at the signal processing engines and data buffers.
However, according to JP2004-236350, the control engine uses the results of checks at respective signal processing engines to perform power consumption control. Accordingly, with an increasing number of signal processing engines, the amount of load on the control engine and each signal processing engine becomes larger.